1. Field of the Invention
Embodiments of the invention relate to switching power supplies, and, in particular, switching power supplies including power factor correction converters.
2. Description of the Related Art
Power factor correction is used for switching power supplies of power rating over 75 W to provide stability and safety in commercial power systems. Recently, a switching power supply has been proposed in Japanese Unexamined Patent Application Publication No. 2007-288855, for example, having a small-sized and highly efficient power factor correction converter (PFC) and a DC-DC converter that converts a DC voltage obtained by the PFC into an output DC voltage according to the specification of the load. The DC-DC converters employed in such switching power supplies are often quasi-resonance converters (QR) in the case of a rated load of about 100 W because of a little burden on a rectifying diode in the secondary side.
FIG. 7 shows a schematic construction of a switching power supply 1 having a power factor correction converter 2 and a DC-DC converter 3 that is a quasi-resonance converter. FIG. 7 also shows a rectifying circuit 4 that rectifies the AC power supplied by the commercial power supply 5 and delivers to the power factor correction converter 2, and a noise filter 6 interposed between the rectifying circuit 4 and the commercial power supply 5.
The power factor correction converter 2 comprises an inductor L1 connected to the rectifying circuit 4, a switching element Q1, and a diode D1. The switching element Q1 forms a current path from the rectifying circuit 4 through the inductor L1 in the ON state of the switching element Q1. The diode D1 forms a current path from the inductor L1 to an output capacitor C2 in the OFF state of the switching element Q1. The power factor correction converter 2 comprises a control circuit IC1 that ON/OFF drives the switching element Q1 to control the current flowing through the inductor L1 thereby obtaining a stable DC voltage Vb.
Resistors R1 and R2 divide the voltage Vb across the output capacitor C2. The divided voltage is fed back to the control circuit IC1. A shunt resistor R3 detects the current flowing through the load of the power factor correction converter 2. The operation and effects of the power factor correction converter 2 as described above are disclosed in detail in Japanese Unexamined Patent Application Publication No. 2010-220330, for example.
The DC-DC converter 3 that is a quasi-resonance converter basically comprises: an isolating transformer T having a primary winding P1, a secondary winding S1, and an auxiliary winding P2; a switching element Q2 connected to the primary winding P1, which receives the output DC voltage Vb of the power factor correction converter 2; a resonance capacitor C4 connected in parallel with the switching element Q2; and an output capacitor C5 connected through a rectifying diode D2 to the secondary winding S1 of the isolating transformer T. The DC-DC converter 3 comprises a control circuit IC2 that ON/OFF drives the switching element Q2 to generate quasi-resonance phenomenon with a leakage inductance of the transformer T and the resonance capacitor C4, thereby obtaining a specified output DC voltage Vo.
The resistances R5 and R6 divide the output DC voltage Vo across the output capacitor C5. The divided voltage is fed back to the control circuit IC2 through a feedback circuit. A shunt resistor R4 detects the current flowing through the switching element Q2. The DC-DC converter 3 detects a ZCD voltage developed on the auxiliary winding P2 of the isolating transformer T and controls the turn ON timing of the switching element Q2. The operation and effects of the DC-DC converter 3 that is a quasi-resonance converter as described above are disclosed in detail in Japanese Unexamined Patent Application Publication No. 2011-015570, for example.
The DC-DC converter 3 is provided with a load condition detecting circuit 7 that detects a load condition and delivers an operation permission signal EN for operation of the power factor correction converter 2 to permit or stop the operation of the power factor correction converter 2. The power factor correction converter 2 is provided with an operation control circuit 8 that permits or stops operation of the power factor correction converter 2 according to the operation permission signal EN. The load condition detecting circuit 7 suspends operation of the power factor correction converter 2 under a light load condition of an input power lower than 75 W, for example, to eliminate any power loss in the power factor correction converter 2. Thus, the overall power conversion efficiency of a switching power supply 1 is improved.
The load condition detecting circuit 7 is constructed as shown in FIG. 8, for example, and installed in the control circuit IC2. The load condition detecting circuit 7 comprises a comparator 7b, which is a light load detecting circuit, and a comparator 7c, which is a middle load detecting circuit. The light load detecting circuit 7b determines a light load condition and sets a flip-flop 7a when the feedback voltage FB, which is used for ON/OFF controlling the switching element Q2 in the DC-DC converter 3, falls below a preset first threshold voltage Vref1. The middle load detecting circuit 7c determines a middle load condition, which is with an ordinary load, and resets the flip-flop 7a when the feedback voltage FB exceeds a second threshold voltage Vref2, which is larger than Vref1 and explained later. The output of the flip-flop 7a is used for set/reset control of a flip-flop 7e after delaying processing through a delay circuit 7d utilizing charging and discharging of a capacitor Ct. Thus, the operation permission signal EN is obtained as a set output of the flip-flop 7e. 
The delay circuit 7d comprises the capacitor Ct and a switching element S connected in parallel with the capacitor Ct. When the output of the flip-flop 7a is in an H level, the switching element S is in an OFF state to charge the capacitor Ct with a constant current source It. When the output of the flip-flop 7a is at an L level, the switching element S is in an ON state to discharge the charges accumulated on the capacitor Ct through the resistor Rt. The load condition detecting circuit 7 comprises comparators 7f and 7g. The comparator 7f resets the flip-flop 7e when the charged voltage Vd on the capacitor Ct exceeds a second reference voltage Vth2; and the comparator 7g sets the flip-flop 7e when the charged voltage Vd falls below a first reference voltage Vth1.
FIG. 9 illustrates waveforms in operation of the load condition detecting circuit 7 having the construction described above. When the load Po becomes lighter and the feedback voltage FB drops below the first threshold value Vref1, the flip-flop 7a is set. According to the setting of the flip-flop 7a, the switching element S in the delay circuit 7d turns OFF and the capacitor Ct is charged with a rate determined by the capacitance of the capacitor Ct and the magnitude of the constant current fed by the constant current source It. After a specified period of time Td-off when the charged voltage Vd of the capacitor Ct exceeds the reference voltage Vth2, the flip-flop 7e is reset and the operation permission signal EN turns to an L level to control the power factor correction converter 2 to stop.
After stop of operation of the power factor correction converter 2, the output voltage Vb of the power factor correction converter 2 gradually decreases and then settles down to a voltage determined by the AC voltage Vac supplied by the commercial power supply 5. The output voltage Vb of the power factor correction converter 2 changes periodically with a period of rectification of the AC voltage Vac and an amplitude determined by the magnitude of the load Po and the capacitance of the output capacitor C2.
In this suspended state of operation of the power factor correction converter 2, when the load Po becomes heavy, the feedback voltage FB in the DC-DC converter 3 rises. When the feedback voltage FB exceeds the second threshold voltage Vref2, the flip-flop 7a is reset and the charges accumulated on the capacitor Ct in the delay circuit 7d are discharged. After a specified period of time Td-on when the charged voltage Vd of the capacitor Ct falls below the reference voltage Vth1, the flip-flop 7e is set to turn the operation permission signal EN to an H level. Consequently, operation of the power factor correction converter 2 is permitted and the power factor correction converter 2 resumes operation.
In the suspended state of the power factor correction converter 2, the DC voltage Vb obtained at the output capacitor C2 of the power factor correction converter 2 changes periodically as described previously with an amplitude determined by the magnitude of the load Po and the capacitance of the output capacitor C2. Accordingly, it has been noted conventionally that the bottom voltage Vb-min of the DC voltage Vb varies depending on the magnitude of the load Po and thus, the second threshold voltage Vref2 for the feedback voltage FB has been set based on the minimum of the DC voltage Vb, the bottom voltage Vb-min.
When the AC voltage Vac is lower than the rated voltage, for example 100 V, or in the case of a small capacitance of the output capacitor C2, even through without large variation in the load Po, the feedback voltage FB rises with decrease in the DC voltage Vb as described earlier. Thus, a situation arises that the feedback voltage FB becomes higher than the second threshold voltage Vref2 that is set based on the minimum of the DC voltage Vb, the bottom voltage Vb-min. This situation causes erroneous detection of increase in the load Po. Thus there is a problem that distinct detection of the rise of the feedback voltage FB that is caused by the increase in the load Po cannot be assured.
FIG. 10 shows a relationship between the feedback voltage FB and the DC voltage Vb depending on the AC voltage Vac in the case of a load Po of a constant value of 30 W, for example. It is shown that the feedback voltage FB increases with decrease in the DC voltage Vb. When the output DC voltage Vb becomes below about 85 V, the feedback voltage FB is always higher than the second threshold voltage Vref2 despite the fact that the load Po is in a light load condition of 30 W constant.
The comparator 7c detects this state to reset the flip-flop 7a, which in turn sets the flip-flop 7e and turns the operation permission signal EN to an H level. Thus, the power factor correction converter 2 changes into an operating state according to the operation permission signal EN despite no change in the magnitude of the load Po. Therefore, it becomes impossible to perform the intended operation in which when the DC voltage Vb decreases with drop of the AC voltage Vac, the power factor correction converter 2 resumes operation thereof after detecting increase in the load Po in a suspended state of the power factor correction converter 2.
To cope with this problem, the second threshold voltage Vref2 could be set relatively high. A high value of the second threshold voltage Vref2, however, makes detection of increased load Po difficult. As a result, when the AC voltage Vac is stable at a sufficiently high value and the operation of the power factor correction converter 2 is suspended, increase in the load Po may not cause operation of the power factor correction converter 2 resume. As a consequence, the DC-DC converter 3 may also fail to adapt to and deal with the increase in the load Po, causing another problem of poor operation of the switching power supply itself. Thus, as has been discussed above, there is a need in the art for an improved switching power supply.